Date of Recording: October 1, 2002
Duration: 60 minutes
Old design "rules of thumb" are no longer valid for multi-gigabit backplane design involving high speeds and fast edge rates. At data rates beyond 1 Gbit/s, new problems arise that backplane designers have to compensate for. The signal integrity of these high-speed serial links is affected by backplane PCB design, connector choice, reflections due to impedance mismatches along the signal path, signal attenuation, crosstalk and Inter Symbol Interference (ISI). As networking, computing and storage applications drive line card data throughput requirements to 40 Gbit/s and beyond, signal integrity is more critical than ever. If you are designing a system with a high-speed serial backplane this webinar is a must.
Peter Wong, Manager, Strategic Marketing, Enterprise & Storage Division, PMC-Sierra
Design Engineers, Engineering Management of Storage Equipment, IT Managers
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