Recorded Event

Date of Recording: October 1, 2002

Duration: 60 minutes

Cost: Free

Designing Dense Multi-Gigabit Serial Backplane Systems

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What to Expect

Old design "rules of thumb" are no longer valid for multi-gigabit backplane design involving high speeds and fast edge rates. At data rates beyond 1 Gbit/s, new problems arise that backplane designers have to compensate for. The signal integrity of these high-speed serial links is affected by backplane PCB design, connector choice, reflections due to impedance mismatches along the signal path, signal attenuation, crosstalk and Inter Symbol Interference (ISI). As networking, computing and storage applications drive line card data throughput requirements to 40 Gbit/s and beyond, signal integrity is more critical than ever. If you are designing a system with a high-speed serial backplane this webinar is a must.

Join us for this webcast and learn about:

  • backplane materials and connectors suitable for high speed designs
  • approaches to modeling a backplane system
  • evaluating jitter performance of a backplane
  • common pitfalls in high speed backplane systems
  • using SERDES to address system requirements

About the Presenter

Peter Wong Peter Wong, Manager, Strategic Marketing, Enterprise & Storage Division, PMC-Sierra

Who Should Attend

Design Engineers, Engineering Management of Storage Equipment, IT Managers

If you have difficulties registering or would like more information about upcoming webinars, email