Product Overview
  • Configurable, multi-channel payload processor for aligning SONET virtual tributaries (VTs) or SDH tributary units (TUs) in an STS-192/STM-64 or STS-48/STM-16 data stream.
  • Supports High Order (STS/AU) pointer processing, payload processing, and path termination/monitoring.
  • Supports Low Order (VT/TU) pointer processing, payload processing, and path monitoring.
  • On the line side, provides working Serial Receive and Transmit ESSI (Extended SONET Serial Interface) CML links. Links are configurable as:
    • 4xSTS-48/STM-16 2488.32 Mbit/s SONET/SDH framed interfaces; or
    • 4xSTS-12/STM-4 622.08 Mbit/s SONET/SDH framed interfaces.
  • On the system side, provides working Add and Drop Serial ESSI links. Links are configurable as:
    • 4xSTS-48/STM-16 2488.32 Mbit/s SONET/SDH framed interfaces; or
    • 4xSTS-12/STM-4 622.08 Mbit/s SONET/SDH framed interfaces.
  • Independently configurable (2488.32 Mbit/s or 622.08 Mbit/s) Line and System Interfaces.
  • Provides a set of Ingress and Egress shared protection links.
  • Provides a per-link Space switch on egress interfaces.
  • Provides a steady-state latency of 20 µs from line Receive to system DROP for VT1.5.
  • Provides hardware based Message Assisted Protection Switching (MAPS) support to work with a centralized fabric (e.g. PM5370 WSE 40).
  • Supports independent Line Receive and System Drop transport frame alignment for high-order traffic.
  • Supports independent transport, high order payload and tributary multi-frame alignments for low-order traffic.
  • Supports independent Line Transmit and System Add transport frame alignments.
  • On the receive path, provides optional SDH payload conversion of:
    • AU4/VC4/TUG3/TU3/VC3/C3 to AU3/VC3/C3; or
    • AU3/VC3/C3 to AU4/VC4/TUG3/TU3/VC3/C3; or
    • AU4/VC4/TUG3/TUG2 to AU3/VC3/TUG2; or
    • AU3/VC3/TUG2 to AU4/VC4/TUG3/TUG2.
  • On the transmit path, provides optional SDH payload conversion of:
    • AU3/VC3/C3 to AU4/VC4/TUG3/TU3/VC3/C3; or
    • AU4/VC4/TUG3/TUG2 to AU3/VC3/TUG2; or
    • AU3/VC3/TUG2 to AU4/VC4/TUG3/TUG2.
  • Allows for low order (VT/TU) processing bypass.
  • Supports high-order ESSI transport overhead transparency.
  • Supports line and system diagnostic and facility loopbacks.
  • Provides optional PRBS generation and monitoring features for ESSI offline link verification.
  • Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring.
  • Provides a standard 5-signal IEEE 1149.1 JTAG test port for boundary scan test purposes.
  • Implemented in a 1.2 V core and 2.5 V I/O 0.13µm CMOS technology. Inputs are 3.3 V tolerant.
  • Packaged in a 672-ball FCBGA, 27 mm x 27 mm.
  • 12 W typical, 15.6 W maximum in OC-192/STM-64 applications using only 2.488 Mbit/s links.
  • 5.4 W typical, 6.9 W maximum in OC-48/STM-16 applications.

Typical Applications include:

  • SONET/SDH Add-Drop Multiplexer (ADM).
  • SONET/SDH Digital Cross-connect (DCC).
  • Multi-service Provisioning Platforms (MSPP).
  • Multi-service ADM (MS-ADM).
  • Multi-Service Switch.
  • Optical Access Mux.
  • Terminal Multiplexers.
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    Product Brief
          Version Issue Date
      PDF Document PM5369 TUPP 9953 Tributary Unit Payload Processor for 9953 Mbit/s Product Brief [365 KB] PMC-2020003 6 2012-03-29
    Data Sheet
          Version Issue Date
    Locked PDF Document TUPP 9953 ASSP Telecom Standard Product Data Sheet [1.44 MB] PMC-2020051 7 2007-01-02
    Application Note
          Version Issue Date
    Locked PDF Document Attaching Passive Heat Sinks to Organic Flip Chip Packages [142 KB] PMC-2020246 3 2007-05-02
    Locked Compressed Document Optimizing Pre-emphasis and Receive Equalization for Backplanes [493 kB] PMC-2021098 1 2002-10-31
    Locked PDF Document SONET/SDH Bit Error Threshold Monitoring [192 KB] PMC-1950820 3 2003-10-15
    White Papers
          Version Issue Date
    Locked PDF Document An Introduction to Transport Networks for Telecommunications [384 KB] PMC-2050808 1 2005-07-20
    Locked PDF Document A Tutorial on SONET/SDH Automatic Protection Switching (APS) [353 KB] PMC-2050248 1 2005-02-15
    Locked PDF Document A Tutorial on SONET/SDH [819 KB] PMC-2030895 3 2005-03-23
    Locked PDF Document Application of Message Assisted Protection Switching (MAPS) to APS Architectures [402 KB] PMC-2021902 3 2003-09-22
    Sales Collateral
          Version Issue Date
    Locked PDF Document Notice of Change - All FCBGA Packages to be Standardized to the HDBU Substrate Package Outline [695 KB] PMC-2062178 1 2006-10-19
    Symbols/Footprints
          Version Issue Date
    Locked Compressed Document PM5369-FI TUPP 9953 672 FCBGA CAD Symbols and Footprints [351 KB] PMC-2051411 1 2005-07-20
    Technical Overview
          Version Issue Date
    Locked PDF Document RASIO 3G for SONET/SDH Backplanes Technology Brief [64 kB] PMC-2030933 1 2003-05-29