Product Overview
  • Monolithic integrated circuit that implements conversion between a byte-serial 77.76 MHz SBI336 bus and a redundant 777.6 Mbit/s bit-serial 8B/10B-based SBI336S bus.
  • SBI converter and TDM time slot interchange.
  • Byte wide 77.76 MHz SBI336 bus to 777.6 MHz serial SBI336S converter.
  • Byte wide 77.76 MHz TelecomBus to serial 777.6 MHz TelecomBus converter.
  • DS0, NxDS0, T1, E1, VT1.5, VT2, DS3 and E3 and STS-1 granular SBI336 to serial SBI336S time slot interchange.
  • VT1.5, VT2, STS-1 77.76 MHz TelecomBus to serial TelecomBus switch. Requires J1 byte alignment.
  • With the Narrowband Switch Element, PM8620 NSE 20G, the SBSLITE can be used to implement a switch fabric scaleable to 20 Gbit/s.
  • With the Narrowband Switch Element, PM8621 NSE 8G, the SBSLITE can be used to implement a switch fabric scaleable to 8 Gbit/s.
  • Integrates two independent DS0 granularity Time Slot Interchange Switches (full duplex).
  • Nominal latency through the SBSLITE in DS0 mode is 125 µS. Channel Associated Signaling (CAS) latency through the SBSLITE in DS0 mode is two T1 multiframes (6 ms) or two E1 multiframes (4 ms).
  • In TelecomBus mode or SBI mode without DS0 level switching nominal latency through the SBSLITE is
  • The Time Slot Interchange Switch permits any receive or incoming byte from an input tributary to be mapped to any outgoing or transmit byte, respectively, on the associated output tributary.
  • Supports working and protect serial SBI336S and TelecomBus links to support a redundant switch fabric architecture.
  • Encodes and decodes byte wide SBI bus and SBI336 bus control signals for all SBI supported link types and clock modes for transport over the serial SBI336S interface.
  • Encodes data from the Incoming SBI bus or TelecomBus stream to working and protect 777.6 Mbit/s LVDS serial links with 8B/10B-based encoding.
  • Decodes data from working and protect 777.6 MHz LVDS serial links with 8B/10B-based encoding to the Outgoing SBI bus or TelecomBus stream.
  • In SBI mode, switches Channel Associated Signaling bits, CAS, with all DS0 data.
  • Uses 8B/10B-based line coding protocol on the serial links to provide transition density guarantee and DC balance and to offer a greater control character vocabulary than the standard 8B/10B protocol.
  • Provides optional PRBS generation for each LVDS serial data link for off-line link verification. PRBS can be processed with minimum STS-1 granularity.
  • Provides hardware and software control to coordinate the connection mapping of the local device, peer SBSLITE devices and companion NSE switch devices.
  • Can communicate with PMC's NSE switch devices over an in-band communications channel in the LVDS links. This channel includes mechanisms for central switch fabric control and configuration.
  • Derives all internal timing from a single 77.76 MHz system clock and a system frame pulse.
  • Supports two sets of switch settings and a controlled method of changing settings on STS-12 frame boundaries.

Typical Applications include:

  • T1/E1 SONET/SDH Cross-connects and Add-Drop Multiplexers.
  • OC-48 Multiservice Access Multiplexers.
  • Channelized OC-12/OC-48 Any Service Any Port Switches.
  • Serial backplane board interconnect and Shelf-to-Shelf cabled serial interconnect.
  • Voice Gateways.

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Product Brief
      Version Issue Date
  PDF Document SBI Bus Serializer /STS-12 Time Slot Interchange Short Form Data Sheet [55 kB] PMC-2010841 4 2001-08-08
Data Sheet
      Version Issue Date
Locked PDF Document SBSLITE ASSP Telecom Standard Product Data Sheet [ -] PMC-2010883 6 2005-12-13
Errata
      Version Issue Date
Locked PDF Document SBSLITE Device Errata [62 KB] PMC-2021310 2 2004-11-03
Locked PDF Document SBS and SBSLITE Device Driver Errata [169 kB] PMC-2021916 1 2003-01-23
Software Documentation
      Version Issue Date
Locked PDF Document NSE/SBS Narrowband Chipset Driver User's Manual [1.25 MB] PMC-2021248 1 2002-09-19
Locked PDF Document SBS and SBSLITE Device Driver Manual [787 kB] PMC-2011471 3 2002-07-10
Software
      Version Issue Date
Locked Compressed Document SBS and SBSLITE Device Driver [275 kB] PMC-2011096 rel 1.0 2002-07-24
Locked Compressed Document CHESS-Narrowband Chipset Driver [621 kB] PMC-2021239 beta 1.0 2002-09-18
Application Note
      Version Issue Date
Locked PDF Document Knowledge Base Items for the PM8611 SBSLITE [113 KB] PMC-2020407 n/a 2005-11-21
Locked PDF Document SBS Board Design Consideration [42 kB] PMC-2011576 1 2001-11-17
Locked PDF Document Cable Length Characterization for Narrowband Devices [121 KB] PMC-2020248 1 2002-07-04
Locked PDF Document CHESS-NB Designing a Non-blocking Fabric for 1:2 Multicast [205 KB] PMC-2020050 2002-03-01
Locked PDF Document CHESS J0/C1 Synchronization and Clock/Frame Pulse Distribution Application Note [415 kB] PMC-2020559 1 2002-11-21
Locked PDF Document CHESS-Narrowband Open Path Algorithm API Design Specification [1.54 MB] PMC-2010601 2 2002-09-19
Symbols/Footprints
      Version Issue Date
Locked Compressed Document PM8611 SBSLITE 160 PBGA CAD Symbols and Footprints [109 KB] PMC-2050839 1 2005-05-02
Technical Overview
      Version Issue Date
Locked PDF Document CHESS Narrowband Chip Set Technical Overview [1.30 MB] PMC-2010865 1 2002-08-01
BSDL Files
      Version Issue Date
  Text Document Boundary Scan Description Language (BSDL) Source Code for the PM8611 Rev. B Device [] PMC-E1982 1 2001-12-18