SWITCHING CAPACITY
- Implements a 64-port memory switch fabric with STS-1/AU-3 switching granularity and scaling capability in a single device.
- With a set of four devices, implements a 640 G 256-port single-stage switch fabric. With a set of two devices, implements a 320 G 128-port single-stage switch fabric.
- Supports non-blocking anycast switching in all single stage configurations.
- Supports fabric capacities greater than 640 G using multi-stage fabrics.
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- Provides two pages of connection memory with software and hardware controlled hitless page swaps at frame boundaries.
- Supports trunk conditioning on a per port, per egress grain basis for AIS and UNEQ insertion.
- Propagation of unselected ingress grains in the device can be optionally disabled to reduce device power consumption.
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SWITCH PORT CONFIGURATION
- Each ingress and egress link can be individually configured to support STS-48 or STS-12 equivalent flows using SONET scrambling over RASIO™ links.
- Interfaces to industry standard components via 622 Mbit/s or 2.188 Gbit/s configured ports.
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- Interfaces to the TBS 2488 and the ARROW family of framers for di-bit, nibble, or byte switching.
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CENTRALIZED OVERHEAD ACCESSIBILITY
- Provides a high bandwidth interface with insert and extract access to all TOH bytes from all ports.
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- Provides a clock and data interface where the number of extracted and inserted TOH bytes is limited to 99 bytes per port selected for each ingress port.
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IMPLEMENTS THE ESSI FRAME LAYER
- Provides in-service link verification via bit interleaved parity (BIP-8) monitoring of the B1 byte.
- Optionally generates standard B1 byte on egress flows.
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- Provides out of frame alignment status information for each ingress port.
- Provides per link SONET-framed and unframed PRBS-23 generation and monitoring for offline link verification.
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GLOBAL FRAME SYNCHRONIZATION
- Provides two independent frame alignment planes.
- Supports frame synchronization using ESSI smart framing or a global frame pulse input signal.
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- Compensates for differences in frame boundary arrival times between ingress ports using FIFOs and device level software configurable delay registers.
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I/O AND GENERAL
- Robust signal integrity over high speed links using PMC-Sierra's RASIO CML I/O for high speed serial ingress, egress, and transport overhead links. RASIO links are E-LVDS comptible.
- Programmable pre-emphasis on transmit, equalization on receiver, and supports both AC and DC coupling.
- Low power 1.2V CMOS core with 2.5V or 3.3V CMOS / TTL selectable digital inputs and outputs.
- Low power consumption.
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- Generic 16-bit microprocessor bus interface for configuration, control, and status monitoring.
- Standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board testing.
- 1152-FCBGA package.
- Includes proprietary Transient Current Demand Management (TCDM)technology that simplifies power supply design.
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Typical Applications include:
Optical Cross-connects.Multi-service Provisioning Platforms.SONET/SDH Digital Cross-connects.SONET/SDH Add/Drop Multiplexers.SONET/SDH Terminal Multiplexers.
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