Features Implements a single chip 12-channel ATM or a bit- HDLC User Network Interface operating at 44.736 Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s. As an ATM interface, it conforms to ATMF-95-1207R1, ATMF-94-0406R5, and AF-PHY-0029.000. For either interface, each line of the S/UNI 12xJET can be individually configured for the desired rate and data formats. Implements a single chip ATM and packet process capable of processing rates up to STS-12c/STM-4-4c payloads. Synchronizes and desynchronizes DS3 and E3 serial streams to or from SONET/SDH payloads, accommodating plesiochronous timing offsets between the line and system timing references, through appropriate processing of bit stuffing and (for desynchronization) pointer movements. Provides a duplex 8-bit 77.76 MHz STS-12/STM-4 line side interface for direct connection to external clock recovery, clock synthesis and serializer-deserializer components. Provides a duplex 8-bit 77.76 MHz TelecomBus-compatible interface, which may be combined with three other S/UNI 12xJET devices to form a 32-bit 77.76MHz STS-48/STM-16 TelecomBus compatible interface. Provides support for SMDS, bit-HDLC and ATM mappings into T3, E3, J2, E1, T1 and arbitrary cell rate transmission systems. Provides termination for SONET Section, Line and Path overhead or SDH Regenerator Section, Multiplexer Section and High Order Path overhead. Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432 on arbitrary SONET/SDH payloads including STS- 1/STM-0/STS-3c/STM-1/STS-12c/STM-4-4c payloads. Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615 and RFC 1662 on arbitrary STS-1/STM-0 payloads. Implements ATM Direct Cell Mapping into DS1, DS3, E1, E3, and J2 transmission systems according to ITU-T Recommendation G.804. Implements bit HDLC Mapping into DS1, DS3, E1, E3, and J2 transmission systems according to ITU-T Recommendation G.804. Implements the Physical Layer Convergence Protocol (PLCP) for DS1 and DS3 transmission systems according to the ATM Forum User Network Interface Specification and ANSI TA-TSY-000773, TA-TSY- 000772, and E1 and E3 transmission systems according to the ETSI 300-269 and ETSI 300-270. Provides on-chip DS3, E3 (G.751 and G.832), and J2 framers.May be configured to be used solely as a DS3, E3, or J2 Framer.Compatible with PMC-Sierra T1/E1 frame/line interface chips for DS1 and E1 applications.Provides programmable pseudorandom test pattern generation, detection, and analysis features.Provides integral transmit data link and receive data link HDLC controllers with 128-byte FIFO depths for each serial channel. Provides support for an arbitrary rate external transmission system interface up to a maximum rate of 52 Mbit/s, which enables any mix of the S/UNI 12xJET's 12 channels for bit-HDLC processing or ATM cell delineation. Provides performance-monitoring counters suitable for accumulation periods of up to 1 second.Provides a 16-bit microprocessor interface for configuration, control and status monitoring.Provides a standard 5-signal P1149.1 JTAG test port for boundary scan board test purposes.Low power 3.3 V / 1.8 V CMOS technology with 5 V tolerant inputs.Available in a high density 580-pin TSBGA package (35 mm x 35 mm) with 1 mm ball pitch.
Typical Applications include:
Multi-service, ATM, SMDS switches, multiplexers and routers.SONET/SDH Mux E3/DS3 tributary interfaces.PDH Mux J2/E3/DS3 line interfaces.J2/E3/DS3 Digital Cross Connect interfaces.J2/E3/DS3 PPP Internet Access interfaces.J2/E3/DS3 Frame Relay interfaces.SONET/SDH ADMs with data processing capabilities.Channelized OC-12 line interfaces in IP routers and Multi-service switches.
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