Features Quad channel ATM and Packet over SONET OC-3c (155 Mbit/s) PHY.Provides on-chip clock and data recovery and clock synthesis.Exceeds Bellcore-GR-253 jitter requirements.Inserts and extracts ATM cells or POS packets into/from SONET SPE.Filters and captures Automatic Protection Switch byes (K1 and K2) and detects APS byte failure.Detects signal degrade and signal failure thresholds crossing alarms.Captures and debounces synchronization status byte (S1).Extracts and inserts the 16- or 64-byte section trace (J0) and path trace (J1) messages.Extracts and inserts section/line data communication channels (DCC).Provides circuitry to meet holdover, wander and long term stability.Provides a generic 8-bit microprocessor interface for device control and register access.Provides standard IEEE 1149.1 JTAG test port for boundary scan.
Typical Applications include:
WAN and Edge ATM SwitchesMultiprotocol SwitchesLayer 3 SwitchesRouters, Packet Switches, and Hubs
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||S/UNI-TETRA [33 kB] PMC-E2012