GENERAL Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 156 Mbit/s for line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 84 T1s, 63 E1s, or 3 DS-3s. Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. Supports 2 levels of priority queueing, with fragment interleaving, in the egress direction for single HDLC channels.
Typical Applications include:
- Wireless Base Station Controllers or Radio Network Controllers.
- Enterprise, Edge and Core Routers.
- Multi-Service Edge aggregation equipment.
- IETF PPP interfaces for routers.
- Frame Relay interfaces for ATM or Frame Relay switches and multiplexers.
- FUNI or Frame Relay service internetworking interfaces for ATM switches and multiplexers.
- Internet/Intranet access equipment.
- Multi-service DSLAM equipment.
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