Product Overview


  • Ten port full-duplex Gigabit Ethernet Controller with an industry standard POS-PHY Level 4 system interface.
  • Provides direct connection to optics.
  • Incorporates ten SERDES, compliant with the IEEE 802.3 1998 PMA physical layer specification.
  • Provides ten standard IEEE 802.3 Gigabit Ethernet MACs for frame verification.
  • Provides on-chip data recovery and clock synthesis.
  • Provides eight unicast exact-match address filters to filter frames based on DA, DA/VID, SA, or SA/VID.
  • Each address filter can indicate whether to accept or discard based on a match.
  • Provides 64-group multicast address filter.
  • Internal 64 kbyte Tx and 224 kbyte Rx FIFOs per channel provisionable in quantities of 1 kbyte to accommodate system latencies.
  • SATURN® compatible interface for Packet-Over-SONET Physical Layer and Link Layer devices Level 4 (POS-PHY Level 4 system interface).
  • Line side loopback for system level diagnostic capability.
  • 16 bit generic microprocessor interface for device initialization, control, register and per port statistics access.
  • Typical Applications include:

  • POS-PHY Level 4 provides consistent system interface for multiple PHY types.
  • Edge and Core Routers.
  • Multi-Service Switches.
  • SONET/SDH Transport Equipment.
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    Product Brief
          Version Issue Date
      PDF Document S/UNIr-10xGE 10-Port Gigabit Ethernet Controller Short Form Data Sheet [85 kB] PMC-2001564 1 2000-10-05
    Reference Design
          Version Issue Date
    Locked PDF Document Xenon PM3388 S/UNI-10xGE Linecard User?s Manual [343 kB] PMC-2030509 1 2003-07-24
    Locked PDF Document S/UNI-10xGE Reference Design [165 kB] PMC-2011425 1 2002-03-22
    Data Sheet
          Version Issue Date
    Locked PDF Document S/UNI Ten-Port Gigabit Ethernet Controller Data Sheet [1.88 MB] PMC-2000340 8 2007-01-02
          Version Issue Date
    Locked PDF Document S/UNI 10xGE Revision B Errata [941 KB] PMC-2011998 4 2005-09-28
    Software Documentation
          Version Issue Date
    Locked PDF Document S/UNI 10xGE Device Driver Manual [798 kB] PMC-2021243 2 2002-12-13
          Version Issue Date
    Locked Compressed Document PM3388 S/UNI 10xGE Device Driver [208 kB] PMC-2021016 Rel 2 2002-12-19
    Application Note
          Version Issue Date
    Locked PDF Document Attaching Passive Heat Sinks to Organic Flip Chip Packages [142 KB] PMC-2020246 3 2007-05-02
    Locked PDF Document PM3388 S/UNI 10xGE Eval Card Reference Design [8.74 MB] PMC-2022022 1 2003-08-01
    Locked PDF Document PM3388 Configuration Guide [368 kB] PMC-2011635 2 2002-10-09
    Locked PDF Document PL4 Static Alignment Design Considerations [197 kB] PMC-2010476 2 2001-07-27
    Locked PDF Document XENON Family Power Supply Filtering Recommendations [42 kB] PMC-2010770 1 2001-06-01
    Locked PDF Document Knowledge Base Items for the PM3388 S/UNI-10x1GE [294 kB] PMC-2020305 2003-10-06
    Locked PDF Document CHESS-II Thermal Management Considerations [529 kB] PMC-2011362 1 2002-07-31
    Sales Collateral
          Version Issue Date
    Locked PDF Document Notice of Change - All FCBGA Packages to be Standardized to the HDBU Substrate Package Outline [695 KB] PMC-2062178 1 2006-10-19
          Version Issue Date
    Locked Input Output Buffer Information Specification (IBIS) Model for the PM3388 S/UNI-10xGE [166 kB] PMC-2011746 1 2001-08-08
    BSDL Files
          Version Issue Date
    Locked PDF Document Boundary Scan Description Language (BSDL) for S/UNI 10xGE [102 kB] PMC-2021223 1 2002-08-29