Features Single chip, dual channel Gigabit Ethernet, SONET/SDH Virtual Concatenation (VC) mapper to STS-48/STM-16 using either frame mapped Generic Frame Procedure (GFP), LAPS/X.86 or BCP/PPP HDLC encapsulation. Provides direct IEEE 802.3 Ethernet lineside connection to optics via two internal Serializer/Deserializer (SERDES) and provides optional connection to Gigabit Ethernet physical layer devices via two GMII interfaces. Supports full-rate and oversubscribed data transfer of Gigabit Ethernet over SONET/SDH with STS-1/VC-3 granularity. Ethernet back-pressure prevents packet loss when SONET/SDH channel is over-subscribed. Provides a total of 92.8 Kbytes of Ethernet ingress buffer and a total of 28.8 Kbytes of Ethernet egress buffer per channel.Supports IEEE 802.3 flow control, autonegotiation, and management statistics.Maps each of two channels of Gigabit Ethernet using frame mapped GFP Ethernet over SONET, LAPS/X.86 or BCP/PPP HDLC encapsulation protocol into a standards-based virtual concatenation stream consisting of between 1 to 8 STS-3c/VC-4 or between 1 to 24 STS-1/VC-3 channels. The VC-3 channels can be either TU-3 mapped or AU-3 mapped. Alternatively maps one Gigabit Ethernet channel into an STS-48c (STM-16/AU-4-16c) channel or maps each Gigabit Ethernet channel into either an STS-24c/STM-8, STS-12c/STM-4, STS-9c, STS-6c, STS-3c/STM-1, STS-1/STM-0, TU-3 (VC-3) channel. Supports on-chip virtual concatenation differential delay buffers of 125 microseconds or off-chip virtual concatenation differential delay buffers of up to 50 milli-seconds using external Quad Data Rate (QDR-I) SRAM interface. Interprets any legal mix of STS (AU-4/AU-3) pointer bytes (H1, H2, and H3), extracts the synchronous payload envelope(s) and processes the path overhead for the receive stream. Generates STS (AU-4/AU-3) pointer bytes (H1, H2, and H3) with offset of 0 (J1 immediately after H3 byte) or 522 (J1 immediately after the J0/Z0 bytes). Inserts the path overhead for the transmit stream. Interprets any legal mix of TU-3 pointer bytes (H1, H2 and H3) extracts the VC-3 synchronous payload envelope(s) and processes the path overhead (both VC-4 and VC-3 for the received data stream). Generates TU-3 pointer bytes (H1, H2 and H3) of offset 0. Inserts both the VC-4 and VC-3 path overhead bytes. Performs full SONET/SDH path termination, including the processing of H4, C2 and J1 bytes for virtual concatenation.Supports GFP Client Management and LAPS/X.86 Control Packet insertion and extraction.Provides working and protect WAN side interfaces. These ports may be configured as 4 x 777.6 MHz eLVDS, 4 x 622 MHz Serial SONET/SDH eLVDS Interface, or 1 x 2.488 Gbps Serial SONET/SDH eLVDS Interface. Supports arbitrary assignment of STS-1 (AU-3) channels via Time Slot Interchange on working and protect WAN side interfaces.Supports mapping and demapping of two Gigabit Ethernet channels into a single STS-48c (STM-16/AU-4-16c) channel via a programmable 32-bit prepend field. Offers per-channel Ethernet side and WAN side loopbacks for system level diagnostic capability.Provides on-chip data recovery and clock synthesis for Gigabit Ethernet and SONET/SDH interfaces.
Typical Applications include:
High density EOS port cards, mapping multiple GE channels into OC-48/STM-16 or OC-192/STM-64 streams.Gigabit Ethernet port cards for Multi-Service Provisioning Platforms..Low power 1.8 V core with 5.0 V tolerant 3.3 V TTL compatible I/O.Non-blocking 128-512 port singlestage fabric Gigabit Ethernet Cross Connect.
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||ARROW-2xGE [67 kB] PMC-E4109