Product Overview

The PM7520 SyntheCLK™ provides multi-output clock generation and distribution using a cascaded phase-locked loop (PLL) architecture with programmable dividers and clock drivers. The Jitter Attenuator (JAT) PLL filters jitter on the incoming reference clock and synchronizes the external voltage controlled crystal oscillator (VCXO). By cascading the Clock Synthesizer PLL with the JAT PLL, this architecture provides clean output clocks using a low cost, low frequency VCXO which is ideal for wireless base station applications requiring highly integrated, low-power clocking solutions.

  • Generates low-jitter, low-phase-noise clock outputs for driving DSP subsystems
  • Provides an output frequency that is SPI programmable for up to 30 clock outputs

Typical Applications include:

  • Low-jitter, low-phase-noise clock distribution
  • Clocking high performance ADCs, DACs, RF Synthesizers, FPGAs
  • High performance wireless transceivers
  • Broadband/Wireless infrastructure
  • Test and measurement (ATE)
  • Multiservice switches/routers
  • Example Application: Multi-Standard Remote Radio Module

    Remote Radio Head (RRH) Application Diagram

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    Product Brief
          Version Issue Date
    Locked PDF Document PM7520 SyntheCLK Low Phase Noise Clock Synthesizer with Integrated Jitter Attenuator Product [224 KB] PMC-2090759 3 2012-02-23
    Data Sheet
          Version Issue Date
    Locked PDF Document PM7520 SyntheCLK Datasheet [7.31 MB] PMC-2090582 6 2011-01-28
    White Papers
          Version Issue Date
      PDF Document Minimizing Delay Uncertainty in Radio Equipment Using JESD204B [857 KB] PMC-2124110 1 2013-05-28
    Locked PDF Document Improving Clock Performance in Base Stations [504 KB] PMC-2103003 1 2011-06-07