The PM7520 SyntheCLK™ provides multi-output clock generation and distribution using a cascaded phase-locked loop (PLL) architecture with programmable dividers and clock drivers. The Jitter Attenuator (JAT) PLL filters jitter on the incoming reference clock and synchronizes the external voltage controlled crystal oscillator (VCXO). By cascading the Clock Synthesizer PLL with the JAT PLL, this architecture provides clean output clocks using a low cost, low frequency VCXO which is ideal for wireless base station applications requiring highly integrated, low-power clocking solutions.
- Generates low-jitter, low-phase-noise clock outputs for driving DSP subsystems
- Provides an output frequency that is SPI programmable for up to 30 clock outputs
Typical Applications include:
Low-jitter, low-phase-noise clock distributionClocking high performance ADCs, DACs, RF Synthesizers, FPGAsHigh performance wireless transceiversBroadband/Wireless infrastructureTest and measurement (ATE)Multiservice switches/routers
Example Application: Multi-Standard Remote Radio Module
Remote Radio Head (RRH) Application Diagram
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