Product Overview
  • Two 933 Mbits/s to 1.25 Gbits/s IEEE 802.3-2000 Gigabit Ethernet and Fibre Channel Physical Interfaces (FC-PI) System Compliant Transceivers.
  • Two secondary serial channels for redundant system design.
  • Integrated clock synthesis, clock recovery, serializer/deserializer, built-in self-test, 8B/10B codec and IEEE 802.3-2000 Gigabit Ethernet Physical Coding Sublayer (PCS) logic.
  • Rate matching via IDLE character insertion and deletion capable of compensating up to ±200 ppm of clock difference between channels.
  • Pin programmable or software configurable operation using 2-pin IEEE 802.3 MDC/MDIO serial management interface.
  • Supports pin-programmable hardware only device configuration.

Typical Applications include:

  • High-speed serial backplanes.
  • IEEE 802.3-2000 Gigabit Ethernet dense line
  • ANSI X3T11 Fibre Channel dense line cards.
  • Link Aggregation.
  • Intra-system and inter-system interconnect.
  • Chassis Extender.
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    Data Sheet
          Version Issue Date
    Locked PDF Document DualPHY 1G ASSP Telecom Standard Product Data Sheet [812 KB] PMC-2040227 1 2004-05-18
      PDF Document DualPHY 1G Standard Product Short Form Data Sheet [46 KB] PMC-2040215 2 2004-09-03
          Version Issue Date
    Locked PDF Document PM8374A DualPHY 1G Revision A Device Errata [60 KB] PMC-2041514 1 2004-08-31
    Application Note
          Version Issue Date
      PDF Document PMC SERDES Introduction Sheet [272 KB] PMC-2040749 1 2004-05-14
      PDF Document Octal/Quad/DualPHY 1G Board Level Design and Debug Tips [171 KB] PMC-2030175 3 2004-07-12