Product Overview
  • High density HDLC controller ideal for Internet access, Frame Relay, and DSLAM equipment supporting rates ranging from 56 Kbit/s to 52 Mbit/s.
  • Supports eight full-duplex and independently-timed links.
  • Supports 128 full-duplex HDLC or transparent channels.
  • Supports a TimePipe architecture that enables any physical link to be flexibly mapped to one or more HDLC channels.
  • Provides 8 KB partial packet FIFO in each transmit and receive direction to compensate for PCI bus latency during data transfers. The 8 KB partial packet FIFO is arranged as 512 blocks of 16-byte buffers.
  • The TimePipe architecture supports programmable assignment of partial packet buffers to HDLC channels.
  • Two physical links can support up to 52 Mbit/s; the remaining six physical links can individually support up to 10 Mbit/s.
  • Supports a mix of channelized and unchannelized links.
  • The maximum aggregate clock rate is 64 MHz. When the device is interfaced to two T3 or HSSI links, the maximum aggregate clock rate is 104 MHz.
  • For channelized operation, the channel assignment supports up to 24 timeslots for a T1 link and 31 timeslots for an E1 link. Timeslots assigned to a common HDLC channel can be noncontiguous.
  • Performs flag delineation, bit de-stuffing, CRC verification using either CRC-32 or CRC-CCITT algorithm, and length checking on receive HDLC channels.
  • Performs flag insertion, bit stuffing, and FCS calculation using either CRC-32 or CRC-CCITT algorithm and length checking on transmit HDLC channels.
  • On the system side, provides a 33 MHz, 32-bit PCI 2.1-compliant bus interface.
  • Implements efficient transmit and receive DMA controllers to support burst data transfers between partial packet FIFO and packet memory.
  • Supports scatter-gather capabilities whereby a packet can span multiple buffers.
  • Supports line-side loopback on a per-link basis and system-side loopback on a per-HDLC channel basis.
  • Pin-compatible and software-compatible with the PM7364 FREEDM 32.
  • Provides a standard 5-signal P1149.1 JTAG test port for boundary scan test board purposes.
  • Implemented in low power 3.3 V CMOS technology with 5 V-tolerant inputs.
  • Packaged in a 256-pin Ball Grid Array (BGA) package.

Typical Applications include:

  • Ideal for applications requiring HDLC, PPP, and transparent protocol processing for physical links, such as T1, E1, T3, E3, xDSL, and HSSI.
  • Frame-Based Interfaces for Internet Access and DSLAM equipment.
  • FUNI or Frame Relay service interworking interfaces for ATM switches and multiplexers.
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    Product Brief
          Version Issue Date
      PDF Document FREEDM-8 Short Form Data Sheet [60 kB] PMC-1970532 4 2001-08-02
    Reference Design
          Version Issue Date
    Locked PDF Document S/UNI-QJET with FREEDM-8 Reference Design [1.39 MB] PMC-1971060 3 1999-02-08
    Data Sheet
          Version Issue Date
    Locked PDF Document FREEDM-8 Data Sheet [2.19 MB] PMC-1970930 4 2001-08-23
          Version Issue Date
    Locked PDF Document FREEDM-8 Revision D & E Device Errata [335 kB] PMC-1980452 10 2003-06-13
          Version Issue Date
    Locked Compressed Document FREEDM-8 Device Driver [64 kB] PMC-E3653 Rev 2.0 2002-04-08
    Application Note
          Version Issue Date
    Locked PDF Document FREEDM-8 Bus Utilization and Latency Test [664 KB] PMC-1970935 2 1997-11-24
    Locked PDF Document Knowledge Base Items for the PM7366 FREEDM-8 [1.05 MB] PMC-2020382 2003-10-06
    Locked PDF Document Pin Differences Between FREEDM-32 and FREEDM-8 [169 kB] PMC-1970957 1 1997-10-10
    Locked PDF Document FREEDM-8 Technical Overview [85 kB] PMC-1970931 2 1998-04-23
          Version Issue Date
    Locked Compressed Document FREEDM8 [17 kB] PMC-E2035 1.09 1999-08-03
    BSDL Files
          Version Issue Date
      Text Document Boundary Scan Description Language (BSDL) Source Code for the PM7366-PI Device [] PMC-2011324 1 2001-06-14
      Text Document Boundary Scan Description Language (BSDL) Source Code for the PM7366 FREEDM-8 Device [] PMC-1980490 1 1998-06-03