GENERAL Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 64 Mbit/s for line-rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 32 T1s, 32 E1s or 1 DS-3. Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. Supports two levels of priority queueing, with fragment interleaving, in the egress direction for single HDLC channels.
Typical Applications include:
- Wireless Base Station Controllers or Radio Network Controllers.
- Enterprise, Edge and Core Routers.
- Multi-Service Edge aggreation equipment.
- IETF PPP interfaces for routers.
- Frame Relay interfaces for Multi-Service Switches.
- FUNI or Frame Relay service interworking interfaces for ATM switches and multiplexers.
- Internet/Intranet access equipment.
- Multi-service DSLAM equipment.
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