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RM7000C
64-bit MIPS RISC Microprocessor with Integrated L2 Cache
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Features
- Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance
- 533, 600 MHz operating frequency
- 1380 Dhrystone MIPS (2.3 DMIPS/MHz @ 600 MHz
- High-performance system interface
- 1280 MB per second peak throughput
- 200 MHz maximum frequency using HSTL signaling on the SysAD bus
- Multiplexed address/data bus (SysAD) supports 1.5 V, 2.5 V, 3.3V I/O logic
- Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
- Integrated primary and secondary caches
- All are 4-way set associative with 32-byte line size
- 16 KB instruction, 16 KB data, 256 KB on-chip secondary
- Per line cache locking in primaries and secondary
- Fast Packet Cache increases system efficiency in networking applications
- Integrated external cache controller (up to 64 MB)
- User-selectable EZ Cache protocol eliminates the need for external tag RAMs.
- High-performance floating-point unit - 1600 MFLOPS maximum
- Single cycle repeat rate for common single-precision operations and some double-precision operations
- Single cycle repeat rate for single-precision combined multiply-add operations
- Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations
- MIPS IV superset instruction set architecture
- Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
- Single-cycle floating-point multiply-add
- Integrated memory management unit
- Fully associative joint TLB (shared by I and D translations)
- 64/48 dual entries map 128/96 pages
- Variable page size
- Embedded application enhancements
- Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three-operand multiply instruction (MUL)
- I&D Test/Break-point (Watch) registers for emulation & debug
- Performance counter for system and software tuning & debug
- Fourteen fully prioritized vectored interrupts - 10 external, 2 internal, 2 software
- Fully static CMOS design with dynamic power down logic
- Pin compatible with RM7000, RM7000A and RM7000B in 304-pin TBGA package, 31x31 mm
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- Fully Static 0.13µ CMOS design with dynamic power down logic
- 304 pin TBGA package, 31x31 mm
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Applications
- Voice Gateways
- Multi-Service Access Platforms
- DSLAMs/Access Concentrators
- Remote Access Switches
- Web Switches
- Layer 3 Switches
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- Backbone Switches/Routers
- RAIDs
- Set Top Boxes
- Networked Printers
- Cellular Base Stations
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RM7000C 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache Short Form Data Sheet [38 KB] PMC-2011604 