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RM7000a™ 64-bit MIPS RISC Microprocessor
Dual-Issue Symmetric Superscalar Microprocessor

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Version Issue Date

Product Brief

PDFRM7000A 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache Short Form Data Sheet [52 kB] PMC-2010739 2  2001-08-10 

Data Sheet

Locked Document, Log In RequiredPDFRM7000A Microprocessor with On-Chip Secondary Cache Data Sheet [553 kB] PMC-2002227 5  2002-08-19 

Errata

Locked Document, Log In RequiredPDFRM7000 Family of Microprocessors Errata [140 KB] PMC-2002295 6  2010-09-09 

Software Documentation

Locked Document, Log In RequiredPDFMIPS IV Instruction Set [1.01 MB] PMC-2010953 3  2001-05-02 
Locked Document, Log In RequiredPDFRM7000 (TM) Family User Manual [4.31 MB] PMC-2002296 1  2001-05-30 

Application Note

Locked Document, Log In RequiredPDFMIPS TLB Operations - Application Note [149 KB] PMC-2031515 2  2004-08-12 
Locked Document, Log In RequiredPDFRM7000 Family Cache Initialization Application Note [64 KB] PMC-2021349 2  2004-04-26 
Locked Document, Log In RequiredPDFKnowledge Base Items for the RM7000A MIPS RISC Microprocessor [822 kB] PMC-2020426   2003-10-06 

Models

Locked Document, Log In RequiredPDFRM7000A [21 kB] 3.04  2001-06-15 

BSDL Files

Text / Binary FileBSDL file for RM7000A PMC-9991000 1  2001-03-29 

Features

  • Dual-Issue symmetric superscalar microprocessor
    • 400MHz max CPU frequency
    • Capable of issuing two instructions per clock cycle
  • Integrated primary and secondary caches
    • 16KB Instruction, 16KB Data, and 256KB on-chip secondary
    • All are 4-way set associative with 32-byte line size
    • Per-line locking in primary and secondary caches
    • Fast Packet Cache increases system efficiency in networking applications
  • Integrated external cache controller
  • Allows up to 8Mbyte of external cache for applications with large data sets
  • High-performance system interface
    • 1000 Mbyte per-second peak throughput
    • 125 MHz max. freq., multiplexed address/data bus (SysAD)
    • Supports two outstanding reads with out-of-order return
  • High-performance floating-point unit: 800 MFLOPS maximum
  • IEEE754 compliant single and double precision floating-point operations
  • 64-bit MIPS instruction set architecture
    • Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
    • Single-cycle floating-point multiply-add
  • Integrated memory management unit
    • Fully associative TLB
    • 64/48 dual entries map 128/96 pages
    • Variable page size
  • Embedded application enhancements
    • Fourteen fully prioritized vectored interrupts-10 external, 2 internal, 2 software
    • Specialized DSP integer Multiply-Accumulate instructions (MAD/MADU), and three-operand Multiply instruction (MUL)
    • I and D Test/Break-point (Watch) registers for emulation and debug
    • Performance counter for system and software tuning and debug

PACKAGING

  • Fully Static 0.18 CMOS design with dynamic power down logic
  • 304 pin TBGA package, 31x31 mm

Applications

  • Voice Gateways
  • Multi-Service Access Platforms
  • DSLAMs/Access Concentrators
  • Remote Access Switches
  • Web Switches
  • Layer 3 Switches
  • Backbone Switches/Routers
  • RAIDs
  • Set Top Boxes
  • Networked Printers
  • Cellular Base Stations
 
 
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