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PM8364 DualPHY 1GR
2 Channel 933 Mbit/s - 1.25 Gbit/s Multi-Protocol SERDES with RGMII Parallel Interface

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Version Issue Date

Product Brief

PDFPM8364 DualPHY 1GR 2-Channel 933 Mbit/s to 1.25 Gbit/s Transceiver Short Form Data Sheet [56 KB] PMC-2040187 2  2004-07-09 

Application Note

PDFPMC SERDES Introduction Sheet [272 KB] PMC-2040749 1  2004-05-14 

Technical Overview

Locked Document, Log In RequiredPDFHardware Design and Configuration Guide for Hex/Quad/DualPHY 1GR [276 KB] PMC-2031039 2  2004-08-04 

Features

GENERAL

  • Two independent 1.0625 to 1.25 Gbits/s IEEE 802.3-2000 Gigabit Ethernet and Fibre Channel Physical Interfaces (FC-PI) System Compliant Transceivers.
  • Integrated clock synthesis, clock recovery, serializer/deserializer, builtin self-test, 8B/10B codec.
  • IEEE 802.3-2000 Gigabit Ethernet Physical Coding Sublayer (PCS) logic.
  • Rate matching via IDLE character insertion and deletion capable of compensating up to ±200 ppm of clock
  • difference between channels.
  • Pin programmable or software configurable operation using 2-pin IEEE 802.3 MDC/MDIO serial management interface.
  • Supports pin-programmable hardware only device configuration.
  • Minimal external components required.
  • 1.5 V and 1.8 V RGMII/RTBI interface.
  • 1.8 V and 2.5 V LVCMOS interoperable for all other digital I/O.

SERIAL INTERFACE

  • High-speed outputs feature programmable output current to optimize drive distance and power - directly drives 50 .. (100 . differential) systems.
  • Integrated 100 . differential resistive termination for a smaller solution footprint, easier layout and improved signal integrity.
  • Direct AC coupled interface to copper serial backplanes, optics and coaxial cable.

PARALLEL INTERFACE

  • 5-bit Dual Data Rate Interface compliant with RGMII/RTBI v2.0 standard.
  • Receive channel output clocks eliminate the need for PLLs in interface ASICs.
  • 1.5 V and 1.8 V HSTL interoperable on RGMII/RTBI digital I/O.

TEST FEATURES

  • IEEE 1149.1 JTAG Boundary Scan support.
  • Built-in self-test (BIST) via internal packet generator/checker.
  • Per-channel control of serial and parallel loopbacks.
  • 8B/10B error counters.

PHYSICAL

  • Ultra-low power operation using 0.18 µm CMOS technology.
  • Thermally enhanced, 196-pin, 15 mm x 15 mm Chip Array BGA package.
  • 1.8 V core and analog power.
  • 1.5 V and 1.8 V interoperable HSTL signals.
  • 1.8 V and 2.5 V interoperable LVCMOS Signals.
  • Designed to operate over a wide temperature range (-40 to +85 °C) and is suited for central office and outside plant equipment.

Applications

  • High-speed serial backplanes.
  • IEEE 802.3-2000 Gigabit Ethernet dense line cards.
  • ANSI X3T11 Fibre Channel dense line cards.
  • Link Aggregation.
  • Intra-system and inter-system interconnect.
  • Chassis Extender.
 
 
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