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PM8354A QuadPHY® 1G
SERDES Interface IC, 4-channel 1.0-1.25 Gbits/s Transceiver
Note: The letter A was added to the product number when the manufacturer changed. Documents written prior to the manufacturer change remain valid.
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Symbols/Footprints
Features
GENERAL
- Four 933 Mbit/s to 1.25 Gbits/s IEEE 802.3-2000 Gigabit Ethernet and Fibre Channel Physical Interfaces (FC-PI) System Compliant Transceivers.
- Four secondary serial channels for redundant system design.
- Configurable as four independent channels or as a single logical trunked channel with deskew providing 4 Gbits/duplex data throughput.
- Integrated clock synthesis, clock recovery, serializer/deserializer, built-in self-test, 8B/10B codec and IEEE 802.3-2000 Gigabit Ethernet Physical Coding Sublayer (PCS) logic.
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- Rate matching via IDLE character insertion and deletion capable of compensating up to ±400 ppm of clock difference between channels.
- Pin programmable or software configurable operation using 2-pin IEEE 802.3 MDC/MDIO serial management interface.
- Supports pin-programmable hardwareonly device configuration.
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SERIAL INTERFACE
- High-speed outputs feature programmable output current to optimize drive distance and power - directly drives 50 Ω (100 Ω differential) systems.
- Integrated 100 Ω differential resistive termination for a smaller solution footprint, easier layout, and improved signal integrity.
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- Direct AC coupled interface to copper serial backplanes, optics, and coaxial cable.
- Low threshold receive differential input threshold.
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PARALLEL INTERFACE
- Single Data Rate (SDR) parallel interface with synchronous receive clock (clock forwarding).
- Half Rate Receive Clock Mode that supports Dual Data Rate.
- Supports GMII and TBI (Ten-bit Interface) standards.
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- Receive channel output clocks eliminate the need for PLLs in interface ASICs
- 1.8 V and 2.5 V interoperable; 3.3 V tolerant.
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TEST FEATURES
- IEEE 1149.1 JTAG Boundary Scan support.
- Built-in self-test (BIST) via internal packet generator/checker.
- Per-channel control of serial and parallel loopbacks.
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- 8B/10B error counters.
- An evaluation kit (PM2376-KIT) is available for the QuadPHY 1G.
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PHYSICAL
- Ultra-low power operation using 0.18 µ CMOS technology.
- Thermally enhanced, 289-pin, 19x19 mm CABGA package.
- 1.8 V core and analog power.
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- I/O voltage configurable as 2.5 V or 1.8 V.
- Designed to operate over a wide temperature range (-40 to +85 °C) and is suited for central office and outside plant equipment.
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Applications
- High-speed serial backplanes.
- IEEE 802.3-2000 Gigabit Ethernet dense line cards.
- ANSI X3T11 Fibre Channel dense line cards.
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- Link Aggregation.
- Intra-system and inter-system interconnect.
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PMC-2051134 PM8354A-NI QuadPHY 1G Rev D 289 CABGA CAD Symbols and Footprints [173 KB]