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PM5357 S/UNI® 622 POS
ATM and Packet Over SONET/SDH SATURN User Network Interface

Documents

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Version Issue Date

Product Brief

PDFS/UNI-622-POS Short Form Data Sheet [105 kB] PMC-1981280 1999-01-15 

Data Sheet

Locked Document, Log In RequiredPDFS/UNI-622-POS Long Form Data Sheet [1.62 MB] PMC-1980911 2002-11-22 

Errata

Locked Document, Log In RequiredPDFS/UNI-622-POS-Data Sheet Errata Notice [81 KB] PMC-1990256 2004-02-09 
Locked Document, Log In RequiredPDFS/UNI-622-POS Reference Design Errata [481 kB] PMC-2001584 2000-12-19 

Software Documentation

Locked Document, Log In RequiredPDFSoftware Driver Manual for the S/UNI-622-POS [235 kB] PMC-1981296 2002-08-27 

Software

Locked Document, Log In RequiredPDFSUNI-622-POS Device Driver [28 kB] Rev 1.0  2002-04-08 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5357 S/UNI-622-POS [1.11 MB] PMC-2020335   2003-10-06 

Models

Locked Document, Log In RequiredPDFS/UNI-622-POS [19 kB] 1.03  1999-08-03 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM5357 S/UNI-622-POS Device PMC-1990711 2000-05-10 

Symbols/Footprints

  Version Issue Date
Locked Document, Log In RequiredZipped FilePMC-2071594 PM5357 S/UNI 622 POS 304 BGA CAD Symbols and Footprints [194 KB]12007-08-02

Features

  • Single chip ATM User-Network Interface operating at 622.08 Mbit/s.
  • Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
  • Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 1619/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF) with the addition of X43+1 payload scrambling.
  • Processes duplex bit-serial 622.08 Mbit/s STS-12c/STM-4-4c data streams with on-chip clock and data recovery and clock synthesis.
  • Supports a duplex byte-serial 77.76 Mbyte/s STS-12c/STM-4-4c line side interface for use in applications where by-passing clock recovery, clock synthesis, and serializer-deserializer functionality is desired.
  • Supports clock recovery by-pass for use in applications where external clock recovery is desired.
  • Provides control circuitry required to comply with Bellcore GR-253-CORE WAN
  • clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
  • Provides UTOPIA Level 2 16-bit wide System Interface (clocked up to 50 MHz) with parity support for ATM applications.
  • Provides UTOPIA Level 3 compatible 8-bit wide System Interface (clocked up to 100 MHz) with parity support for ATM applications.
  • Provides SATURN POS-PHY Level 2TM 16-bit System Interface (clocked up to 50 MHz) for Packet over SONET (POS) applications. This system interface is similar to UTOPIA Level 2, but adapted to packet transfer.
  • Provides SATURN POS-PHY Level 3TM 8-bit System Interface (clocked up to 100 MHz) for Packet over SONET (POS) applications.
  • Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
  • Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
  • Low power 3.3V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3V and 5V compatible.
  • Industrial temperature range (-40°C to +85°C).
  • 304 pin Super BGA package.

Applications

  • WAN and Edge ATM switches
  • LAN switches and hubs
  • Packet switches and hubs
  • Routers and Layer 3 Switches
  • Network Interface Cards and Uplinks
 
 
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