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PM5326 ARROW 2x192
SONET/SDH Transport Framer/Aggregator for OC-48 and OC-192

Documents

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Version Issue Date

Product Brief

PDFPM5326 ARROW-2x192 SONET/SDH Transport Framer/Aggregator for OC-48 and OC-192 Short Form Data Sheet [49 KB] PMC-2001648 2005-03-18 

Application Note

Locked Document, Log In RequiredPDFAttaching Passive Heat Sinks to Organic Flip Chip Packages [142 KB] PMC-2020246 2007-05-02 
Locked Document, Log In RequiredPDFOptimizing Pre-emphasis and Receive Equalization for Backplanes [493 kB] PMC-2021098 2002-10-31 
Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5326 ARROW-2x192 [268 kB] PMC-2020644   2003-10-06 

White Papers

Locked Document, Log In RequiredPDFAn Introduction to Transport Networks for Telecommunications [384 KB] PMC-2050808 2005-07-20 
Locked Document, Log In RequiredPDFA Tutorial on SONET/SDH Automatic Protection Switching (APS) [353 KB] PMC-2050248 2005-02-15 
Locked Document, Log In RequiredPDFA Tutorial on SONET/SDH [819 KB] PMC-2030895 2005-03-23 
Locked Document, Log In RequiredPDFApplication of Message Assisted Protection Switching (MAPS) to APS Architectures [402 KB] PMC-2021902 2003-09-22 

Sales Collateral

Locked Document, Log In RequiredPDFNotice of Change - All FCBGA Packages to be Standardized to the HDBU Substrate Package Outline [695 KB] PMC-2062178 2006-10-19 

Models

Locked Document, Log In RequiredPDFFLOTHERM Detailed Model for PM5326 packaged in a 37.5 mm 1292 Pin FCBGA at assembler 'N' [3 KB] PMC-2042404 2004-12-14 

Technical Overview

Locked Document, Log In RequiredPDFRASIO 3G for SONET/SDH Backplanes Technology Brief [64 kB] PMC-2030933 2003-05-29 

Symbols/Footprints

  Version Issue Date
Locked Document, Log In RequiredZipped File PM5326 ARROW 2x192 1292 BGA OrCAD Symbol and Footprint [173 KB]12008-02-29

Features

  • Dual SONET/SDH framer/aggregator for use in channelized STS-192/STM-64 and STS-48/STM-16 applications.
  • 20 Gbit/s aggregate capacity. Each of the two framers within the device can be independently configured to support:
    • One STS-192/STS-192c/STM-64/STM-64c stream.
    • Four STS-48/STS-48c/STM-16/STM-16c streams.
  • Supports two STS-192/STM-64 streams via two standard OIF SFI-4 interfaces (duplex 16-bit 622 MHz LVDS) for direct connection to SERDES and CRU/CSU devices.
  • Supports up to eight STS-48/STM-16 via SFI-4 interfaces operating in nibble mode.
  • Provides two sets of working, protect, and APS interfaces for connection across system backplanes. Each interface consists of four ESSI (Extended SONET Serial Interface) CML links, operating at 2.488 Gbit/s.
  • Supports channelized (down to STS-1), concatenated, and arbitrarily concatenated (STS-3cxN) traffic. Changes in traffic configurations are automatically detected.
  • Terminates (or monitors) SONET/SDH Section, Line, and Path overhead and provides STS-1 granularity frame alignment and pointer processing.
  • Detects and inserts transport and path BIP-8 errors (B1, B2, B3). Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms for B2 and B3.
  • Provides overhead passthrough for entire TOH, and re-mapping for B1, B2, and J0 bytes.
  • Provides dedicated pins to extract and reinsert the entire transport overhead.
  • Provides dedicated pins to extract section and line DCC.
  • Supports Automatic Protection Switching:
    • K1/K2 byte filtering and BER monitoring.
    • Direct line card APS connections via system side APS ports.
  • Supports centralized control of SONET/SDH processing by providing in-band status messaging (Transport, Path, and Equipment Status) on the ESSI ports.
  • Provides independent STS-1 Memory Switching Units (MSU) for combined time-slot interchange (TSI) and muxing functions in transmit and receive directions.
  • Provides independent STS-1 Memory Switching Units (MSU) at the DROP APS port for grooming traffic to support line card pairing or local traffic termination.
  • Can be configured in line to line mode (SFI-4 to SFI-4) while independently adding/dropping traffic to/from working and protect system interfaces:
    • Supports STS-192/STM-64 or STS-48/STM-16 passthrough, or aggregation of 4xSTS-48/STM-16 via SONET multiplexing or byte interleaving.
  • Provides line loopback from the line side receive streams to the transmit streams and supports diagnostic loopback on the system side interface.

GENERAL

  • General purpose 16-bit microprocessor interface for configuration, control, and status monitoring.
  • Low power 1.2 V core with 2.5/3.3 V I/O.
  • Standard 5-signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
  • 1292-pin FCBGA package.

Applications

  • Multi Service Provisioning Platforms (MSPP).
  • Sub Wavelength Cross Connects.
  • Add/Drop Multiplexers.
  • DWDM Platforms.
  • Channelized Routers and Multi Service Switches.
 
 
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