UPCOMING WEBINAR

A Tutorial on Double Data Rate (DDR) SDRAM

WHAT TO EXPECT
Synchronous Dynamic Random Access Memory (SDRAM) devices are volatile memories that are synchronized to the system clock. They offer low cost per bit solutions and are used often as Main Memory in a system. Double Data Rate (DDR) SDRAM further increases system performance by doubling the data rate and has become a popular memory choice for PCs, servers and embedded processor systems.

This webinar will:

ABOUT THE PRESENTER
Karl Scheffer, Sr. Design Engineer, Communications Products Division, PMC-Sierra

Karl Scheffer is a Senior Product Design Engineer in PMC-Sierra's Communications Products Division. Since joining PMC-Sierra in 1999, Mr. Scheffer has been developing high-speed digital designs including delay locked loops, clock recovery units, and clock synthesis units. He has also been involved with developing elements of PMC-Sierra's DDR-SDRAM interface.

Mr. Scheffer has over 7 years experience in the telecommunications and high technology industries. In 1997, Mr. Scheffer graduated with a Bachelor's of Applied Science in Electrical Engineering with Honors from Simon Fraser University.

WHO SHOULD ATTEND
Design engineers, system architects, product line managers, engineering management and marketing managers of embedded systems and other processor based equipment.

Click here to register for webinar

If you would like more information about upcoming webinars, please email webinars@pmc-sierra.com.

RECENTLY ARCHIVED WEBINARS

SAS Access Control Zoning Tutorial

WHAT TO EXPECT
Storage innovations, such as SAS Expanders, increased capacity and increased accessibility have introduced risks that can threaten the availability, integrity and confidentiality of today's storage infrastructures. SAS expanders are high-speed switches that enable a single SAS domain to contain over 16,000 storage drives (SAS and/or SATA). It is important to have an access control mechanism in place for the SAS expander to ensure security among the devices.

This webinar:

• Summarizes the growing importance of storage security
• Explains the need for SAS expanders to support Access Control Zoning
• Details PMC-Sierra's Access Control Zoning implementation and its benefits

Click here to view

SoC Benefits Tutorial

WHAT TO EXPECT

Click here to view

04/12/05
PMC-Sierra Delivers maxSAS Reference System for Enterprise SATA/SAS Storage Enclosures

PMC-Sierra, Inc. announced the availability of the PM2319-KIT maxSAS(TM) Reference System for fabric attached and server attached SATA/SAS disk array enclosures. The Reference System, combined with the SCSI Enclosure Services (SES) Software Development Kit (SDK) significantly reduces development costs while accelerating time-to-market for storage equipment vendors.

Click here to read

PMC-Sierra Reports First Quarter 2005 Results

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PMC-Sierra and Environmental (RoHS) Compliance

In 2002 the European Union (EU) issued a directive on the Restriction of Hazardous Substances (RoHS) for product packaging. Since that time, PMC-Sierra has been working to qualify the majority of our package types to meet these environmental requirements.

Our customers are now asking for RoHS Compliant products and PMC-Sierra is ready. We developed information on our website stating our position, issued a Material Declaration Certificate, and developed an FAQ page. In fact, we have already shipped RoHS compliant products to customers - well ahead of the 2006 EU-directive deadline.

PMC-Sierra's RoHS Compliance Web Page

If you have a question that is not answered on our web page, e-mail us.

Resilient Packet Ring (RPR) Technology
The two basic motivations behind RPR are: 1) more reliable data communications and 2) extending life of the current telecommunications networks. On the data communications side, there was a desire for a broadband MAN/WAN protocol that used rings to provide higher reliability. On the telecommunications side, there was a desire to extend the concept of a TDM add/drop multiplexer to the packet world. PMC-2041096 Issue 1

Generic Framing Procedure (GFP)
GFP was developed to allow efficient transport of packet data through SONET/SDH networks, making use of the new virtual concatenation and LCAS technologies for creating flexible-sized transport channels. GFP is covered in depth in this white paper since it is not covered in any existing books. PMC-2041083 Issue 2

A Guide to Processor Bus Fundamentals
This paper describes some of the common characteristics of today's processor busses and it provides an overview of the top three major public bus standards (PCI Express, HyperTransport, and RapidIO). It also provides a brief overview of internal bus standards (Fast Device Bus (FDB), AMBA, and OCP) and describes some of the challenges that designers need to consider before implementing a bus in their design. Also included is a brief summary of how some of PMC-Sierra's newer SoC products use processor busses. This paper is a companion document to the PMC-Sierra webinar by the same name. PMC-2042530 Issue 1

In-Service T1/E1 Performance Monitoring
This paper describes in-service PMON of T1/E1 networks, from current deployment in overlay networks to integration in next generation transport equipment. It identifies how next generation T1/E1 framing devices will support in-service PMON. PMC-2042530 Issue 1

China VoIP
Beijing, China
May 17 to 19, 2005

PMC Sierra's Vice President of Marketing for the Communications Product Division, Dino Bekis, presented on "Carrier requirements for VoIP" at the 2005 China VoIP & Expo in Beijing on May 18th. Dino introduced the factors that affect voice and call quality in a VoIP service. He addressed key issues such as the cost / quality trade-offs in Residential CPE equipment, the technical hardware and software challenges in developing a PSTN replacement system and how these challenges can be overcome with today's solutions. At the event, PMC-Sierra demonstrated a new VoIP Analog Telephone Adapter solution - a complete turnkey design providing Carrier-Class quality. The company also announced that its VoIP technology has been certified as Best-In-Class by the China Telecommunication Technology Labs and Korea's Telecommunications Technology Association.

Supercomm
June 7 to 9, 2005
Booth # 59078, McCormick Place, Chicago, IL

See PMC-Sierra's Triple Play at Supercomm article under Communications Highlights

Design Automation Conference (DAC)
June 13-17
Anaheim, California

The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. Norbert Diesing, Director of Technology Access presented "How to Choose from All the Process Nodes, IP Cores, and Other SoC Suppliers"

Embedded Systems Expo and Conference
Japan's largest embedded systems technology expo & conference
June 29 to July 1, 2005
Booth #5-30
Tokyo, Japan

PMC-Sierra will be exhibiting at the upcoming Embedded Systems Expo & Conference (ESEC) show in Tokyo, Japan from June 29 to July 1. The company will be showcasing its portfolio of MIPS-Powered processor solutions, ideal for laser printer, networking, storage and customer presises equipment applications.

PMC-Sierra, Wintegra to develop networking system solutions

Electronic Engineering Times VIEW

PMC-Sierra Announces Production Release of CHESS III and CHESS Wideband Chip Sets

CanadaIT.com VIEW

PMC-Sierra Offers Wireless-Capable Voice Over Ip 'Router On A Chip'

LinuxElectrons ™ VIEW

Complete CPRI reference design for 3G base station interconnects

3G Newsroom VIEW (Registration Required)

PMC-Sierra's TEMAP 168 cuts cost of voice & data services while handling high-density mapping

PMC Sierra introduces its PM8313 TEMAP 168, the industry's highest density transmultiplexing and PDH mapper solution.

Lightwave VIEW
networkZONE VIEW
EETimes (Registration Required) VIEW

PMC-Sierra introduces its highly
integrated PM2337 ADM 622 Evaluation Platform

PMC Sierra's PM2337 ADM 622 is a stand-alone, user friendly, complete schematic design Evaluation Platform.

LinuxElectrons™ VIEW
Lightwave VIEW

MIPS Technologies Introduced the MIPS32® 24KE™ Core Family - the First DSP ASE Enabled MIPS® Cores

The 24KE core family leverages the high performance 24K™ micro architecture and efficiently adds DSP functionality while significantly reducing overall SoC die area, cost, and power consumption.

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MIPS Technologies Names Wind River as its Premier Device Software Optimization Solution Provider

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CoWare and MIPS Technologies to Automate Application-Optimized Processor Creation

New CoWare CORXpert™ Enables SoC Designers to Easily Develop Instructions for MIPS® Processors for Increased Product Performance

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PMC-Sierra's Chinese, Japanese and Korean Language Websites At Your Fingertips

PMC-Sierra offers you the ability to search for product information, documentation and more in 3 languages - Chinese, Japanese and Korean.

To find out more, visit:
Chinese: http://pmcs.com/zh/

Japanese: http://pmcs.com/

Korean: http://pmcs.com/